
33 Appendix A
A.4 Digital Output
A.5 Counter/Timer
Output Channels
16
Output Voltage
Low 0.8 V max.@ +8.0mA (sink)
High 2 V min.@ -0.4mA(source)
Counter chip
82C54 or equivalent
Channels
3 channels, 2 channels are permanently configured as
programmable pacers; 1 channel is free for user appli-
cation
Resolution
16-bit
Compatibility
TTL level
Base Clock
Channel 2: Takes input from output of channel 1
Channel 1: 10MHz
Channel 0: Internal 1MHz or external clock (10 MHz)
max Selected by software
Max. Input
Frequency
10MHz
Clock Input
Low 0.8 V max.
High 2.0 V min.
Gate Input
Low 0.8 V max.
High 2.0 V min.
Counter Output
Low 0.5 V max.@+24 mA
High 2.4 V min.@-15 mA
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