Advantech PCI-1718 Instrukcja Użytkownika Pobierz pdf (Strona 81)

73 Appendix C

C.13 A/D Control — BASE+09H

Read/write register BASE+09H provides information on the PCI-

1718HDU/HGU's operating modes.

INTE Disable/enable generated interrupts

0 Disables the generation of interrupts. No interrupt signal can be sent

to the PC bus.

1 Enables the generation of interrupts. If DMAE = O the PCI-1718

card will generate an interrupt when it completes an A/D conversion.

Use this setting for interrupt driven data transfer.

If DMAE = 1 the PCI-1718HDU/HGU will generate an interrupt when it

receives a T/C (terminal count) signal from the PC's DMA controller,

indicating that a DMA transfer has completed.

Use this setting for DMA data transfer. The DMA transfer is stopped by

the interrupt caused by the T/C signal. See DMAE below.

ST1 to ST0 Trigger source

Table C.15: Register for A/D Control

Read/Write A/D control

Bit # 76543210

BASE + 09H INTE ST1 ST0

Trigger source ST1 ST0

Software trigger 0 X

External trigger 1 0

Pacer trigger 1 1

1 2 ... 76 77 78 79 80 81 82 83 84 85 86 ... 93 94

Brak uwag

Advantech PCI-1718 Instrukcja Użytkownika Strona 81