Advantech PCI-1739U Instrukcja Użytkownika Pobierz pdf (Strona 38)

PCI-1737U/PCI-1739U User Manual 28

4.2.3 Initial Configuration

The initial configuration of each port depends on the switch setting

(SW1/SW2 for PCI-1737U and SW1/SW2/SW3/SW4 for PCI-1739U)

If SW1 is set to “OFF” , all ports configured by software are automati-

cally set as input ports during system start up or reset, with a default sig-

nal level of logic 1 (high). All ports are set as output ports during system

start up or reset when SW1 is set to “ON”, signal level depends on SW2.

If SW2 is set to “OFF”, the corresponding port will be set logic 1 (voltage

high), otherwise, they will be set logic 0 (voltage low). Refer to "Switch

Settings" in Chapter 2 for more information.

4.3 Interrupt Handling

Two lines in the I/O port (C0 and C4) are connected to the interrupt cir-

cuitry. The "Interrupt Control Register" of the PCI-1737U/PCI-1739U

controls how the combination of the two signals generates an interrupt.

When the interrupt request signal is generated, the software can service

the request signal by ISR.

4.3.1 IRQ Level

The IRQ level is set automatically by the PCI plug-and-play BIOS and is

saved in the PCI controller. There is no need for users to set the IRQ

level.

4.3.2 Interrupt Control Register (Base + 8)

The "Interrupt Control Register" (Base + 8) controls the interrupt signal

source, edge and flag. Table 4-2 shows the bit map of the interrupt control

is used as a control register, and when reading from it, it is used as a status

Table 4.2: Interrupt control register bit map

D7 D6 D5 D4 D3 D2 D1 D0

Read0000F0E0M01M00

Write N/A

1 2 ... 33 34 35 36 37 38 39 40 41 42 43 44 45 46

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