Advantech PCI-1720 Instrukcja Użytkownika Pobierz pdf (Strona 31)

Chapter 4 Register Structure and Format 27

4.7 Control Register  BASE+6

The write-only register BASE+6 allows users to set an A/D trigger

source and an interrupt source.

Table 4-6: Control register

SW Software trigger enable bit

Set 1 to enable software trigger, and set 0 to disable.

PACER PACER trigger enable bit

Set 1 to enable pacer trigger, and set 0 to disable.

EXT External trigger enable bit

Set 1 to enable external trigger, and set 0 to disable.

Note!: Users cannot enable SW, PACER and EXT concurrently.

GATE External trigger gate function enable bit

Set 1 to enable external trigger gate function, and set 0 to disable.

IRQEN Interrupt enable bit

Set 1 to enable interrupt, and set 0 to disable.

ONE/FH Interrupt source bit

Set 0 to interrupt when an A/D conversion occurs, and set 1 to

interrupt when the FIFO is half full.

Write Control Register

Bit # 7 6 5 4 3 2 1 0

BASE + 6 ONE/FH IRQEN GATE EXT PACER SW

1 2 ... 26 27 28 29 30 31 32 33 34 35 36 ... 53 54

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Advantech PCI-1720 Instrukcja Użytkownika Strona 31