Advantech PCI-1739U Instrukcja Użytkownika Pobierz pdf (Strona 39)

29 Chapter 4

M00 and M01: mode bits of port0

E0: triggering edge control bits

F0: interrupt flag bit

4.3.3 Interrupt Source Control

The "mode bits" in the interrupt control register determine the allowable

sources of signals generating an interrupt. Bit 0 and bit 1 determine the

interrupt source for port. Table 3-3 shows the relationship between an

interrupt source and the values in the mode bits.

4.3.4 Interrupt Triggering Edge Control

The interrupt can be triggered by a rising edge or a falling edge of the

interrupt signal, selectable by the value written in the "triggering edge

control" bit in the interrupt control register, as shown in Table 4-4.

Table 4.3: Interrupt mode bit values

Port0

M01 M00 Description

0 0 Disable interrupt

0 1 Source=PC00

1 0 Source=PC00 when PC04 =0 ;

INT disable when PC04 = 1

11N/A

Table 4.4: Triggering edge control bit values

E0 Triggering edge of interrupt signal

1 Rising edge trigger

0 Falling edge trigger

1 2 ... 34 35 36 37 38 39 40 41 42 43 44 45 46

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