Advantech PCI-1718 Series Instrukcja Użytkownika Pobierz pdf (Strona 63)

55 Appendix A

A.5 Counter/Timer

Counter chip

82C54 or equivalent

Channels

3 channels, 2 channels are permanently configured as

programmable pacers; 1 channel is free for user appli-

cation

Resolution

16-bit

Compatibility

TTL level

Base Clock

Channel 1: 10 MHz

Channel 2: Takes input from output of channel 1

Channel 0: Internal 100 kHz or external clock

(10 MHz max.) selected by software

Max. Input

Frequency

10 MHz

Clock Input

Low 0.8 V max.

High 2.0 V min.

Gate Input

Low 0.8 V max.

High 2.0 V min.

Counter Output

Low 0.5 V max.@+24 mA

High 2.4 V min.@-15 mA

1 2 ... 58 59 60 61 62 63 64 65 66 67 68 ... 93 94

PCI-1718 Series 1
User Manual 1
Contents 5
Introduction 9
Chapter 1 Introduction 10
1.1 Features 11
1.2 Applications 12
1.3 Installation Guide 13
PCI-1718 Series User Manual 6 14
1.4 Software Overview 15
PCI-1718 Series User Manual 8 16
9 Chapter 1 17
1.6 Accessories 18
Installation 19
Chapter 2 Installation 20
2.2 Driver Installation 21
2.3 Hardware Installation 23
17 Chapter 2 25
Signal Connections 27
Chapter 3 Signal Connections 28
23 Chapter 3 31
Jumper Function description 31
JP10 5 V (default) 31
JP8 1 MHz (default) 32
27 Chapter 3 35
Reset status after hot reset 35
(default) 35
3.3 Signal Connections 36
31 Chapter 3 39
33 Chapter 3 41
35 Chapter 3 43
Programming Guide 45
Chapter 4 Programming Guide 46
39 Chapter 4 47
41 Chapter 4 49
43 Chapter 4 51
45 Chapter 4 53
47 Chapter 4 55
49 Chapter 4 57
Specifications 59
Appendix A Specifications 60
A.2 Analog Output 61
A.3 Digital Input 62
A.4 Digital Output 62
A.5 Counter/Timer 63
A.6 General 64
Block Diagrams 65
Appendix B Block Diagrams 66
Register Structure & 67
C.1 Overview 68
C.2 I/O Port Address Map 68
65 Appendix C 73
Write A/D range control 73
Bit # 76543210 73
BASE + 01H XXXXG3*G2*G1G0 73
67 Appendix C 75
Bit # 7 6543210 75
C.9 D/A Output — BASE+04/05H 77
Write FIFO interrupt control 78
Bit # 7 654321 0 78
C.12 A/D Status — BASE+08H 79
C.13 A/D Control — BASE+09H 81
Write Timer/Counter enable 82
BASE + 0AH TC1 TC0 82
C.18 FIFO Status — BASE+19H 84
C.19 FIFO Clear — BASE+19H 84
77 Appendix C 85
79 Appendix C 87
Calibration 89
Appendix D Calibration 90
D.1 VR Assignment 91
D.2 A/D Calibration 92
D.3 D/A Calibration 93

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