Advantech PCI-1753E Instrukcja Użytkownika Pobierz pdf (Strona 28)

PCI-1753/1753E User Manual 22

Mn0 and Mn1: “mode bits” of port Cn (n = 0 ~ 3)

M1: pattern match port enable control bit of port A0

M2: change of state port enable control bit of port B0

En: triggering edge control bit (n = 0 ~ 3)

Fn: interrupt flag bit of port Cn (n = 0 ~ 3)

F01: pattern patch interrupt flag bit of port A0

F02: change of state interrupt flag bit of port B0

Table 3.2: Interrupt control register bit map

Base+16/48 Port 0

Bit # D7D6D5D4D3D2D1D0

Abbreviation F0 E0 M01 M00 F02 M2 F01 M1

Base+17/49 Port 1

Bit # D7D6D5D4D3D2D1D0

AbbreviationF1E1M11M10----

Base+18/50 Port 2

Bit # D7D6D5D4D3D2D1D0

AbbreviationF2E2M21M20----

Base+19/51 Port 3

Bit # D7D6D5D4D3D2D1D0

AbbreviationF3E3M31M30----

1 2 ... 23 24 25 26 27 28 29 30 31 32 33 ... 41 42

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Advantech PCI-1753E Instrukcja Użytkownika Strona 28